Numerous industry trends are leading chip designers to consider multi-die designs using advanced 2.5D and 3D technologies. Such designs enable the integration of heterogeneous and homogeneous chips into a single package, increasing density and reducing signal propagation times. However, multi-die designs introduce new challenges that must be addressed by all relevant Electronic Design Automation (EDA) and IP products in the design flow. Perhaps the biggest impact is the implementation tools that convert the Register Transfer Level (RTL) design into manufacturable layouts.

This white paper explains how Synopsys UCIe IP and 3DIC Compiler integrate to deliver a pre-validated and tested design reference flow with all required design deliverables such as automated routing flow, interposer studies, and signal integrity analysis. The combination of the products helps designers efficiently integrate chips and jointly optimize thermal and power integrity to ensure design feasibility and accurate clearance for system-level effects.

Read more here.

Fig. 1: UCIe in the interposer view in the Synopsys 3DIC compiler.